makefile - Make always rebuilding dependencies -

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when use makefile without variable targets, things work fine

preamble:         mkdir -p data         touch $@  data/a: preamble         touch $@  data/b: data/a         touch $@  data/c: data/a         touch $@  data/d: data/b data/c         touch $@  diamond: data/a data/b data/c data/d         touch $@  .phony: clean clean:         rm -rf ${data} diamond preamble

however, when introduce target variable tasks involved run.

data="data" preamble:         mkdir -p ${data}         touch $@  ${data}/a: preamble         touch $@  ${data}/b: data/a         touch $@  ${data}/c: data/a         touch $@  ${data}/d: data/b data/c         touch $@  diamond: ${data}/a ${data}/b ${data}/c ${data}/d         touch $@  .phony: clean clean:         rm -rf ${data} diamond preamble

these executed

touch "data"/a touch "data"/b touch "data"/c touch "data"/d touch diamond

what correct way include variables in target?

i recommend not using quote marks. makefile not need them, , confusing file names.

it more common $(data) parenthesis instead of ${data} curly braces.

also, matter of practice, recommend using variable names in caps. call data instead of data.


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