I'm trying to write a code for counter using vhdl -

this vhdl code synchronous type counter. i'm still new in vhdl, i'm having problem in writing testbench simulate code. can give me suggestions on how write testbench? thank you

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity cnt4     port( clk, rst  : in std_logic;           q         : out std_logic); end cnt4;  architecture ex1 of cnt4 signal cnt : std_logic_vector(1 downto 0);  begin     process(clk, rst)     begin         if rst = '1'             cnt <= "00";         elsif clk'event , clk = '1'             if cnt = 3                 cnt <= "00";                 q <= '1';             else                 cnt <= cnt + 1;                 q <= '0';             end if;         end if;     end process; end ex1; 

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this testbench i've tried write far

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity testbench  end testbench;  architecture ex1 of testbench     signal clk, rst : std_logic;     signal q        : std_logic;      component cnt4         port( clk, rst : in std_logic;               q        : out std_logic );     end component;  begin     u0: cnt4 port map(clk, rst, q);      process     begin         clk <= '1';         wait 10 ns;         clk <= '0';         wait 10 ns;         wait;     end process;      process     begin         rst <= '0'; wait 10 ns;         rst <= '1'; wait 10 ns;          wait;     end process; end ex1; 

the simulation result using testbench above in picture

simulation

it may ridiculous don't know how write testbench. glad if can me