what is the real meaning of #10 verilog testbench? -

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i new in verilog programming. trying explore meaning of simple mux code. in test bench, observed there multiple " #10 "s. purpose of line?

also please explain need of defining inputs "reg" , output "wires"

i have added snapshot reference.

tb image in advance.

vt

it adds 10 units of time delay before executing statement.

@always(clock.posedge) begin     #10     c = + b end

the above example adds , b after 10 units of delay posedge of clock


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